module daughter2ctrl
			(
/*
================================================================================
Beggining of user changeable code
Part 1. IO description
*/
			 clock, resetn,
			 DIN_LTAODD, DIN_LTAEVEN,
			 DIPSWn,

			 ROW_ADDR,
			 gRESET_PIXELn, PHI1, PHI2, PHI3, PHI4, RESET_SUM,
			 RESET_LOGICn,
			
			 LATCH_LTAOUTn, ADV_LTAOUTn,
		
			 POD_CLK, POD_DB,
			
			 CSn, STARTn,
			 RDn,
			 SEL, DB,
			 
			 ADC0_CSn, ADC0_DCLK, ADC0_DIN,
			 ADC1_CSn, ADC1_DCLK, ADC1_DIN
			);

input			clock, resetn;
input			DIN_LTAODD, DIN_LTAEVEN;
input	[7:0]	DIPSWn;
output	[1:0]	ROW_ADDR;
output			gRESET_PIXELn, PHI1, PHI2, PHI3, PHI4, RESET_SUM;
output			RESET_LOGICn;

output			LATCH_LTAOUTn, ADV_LTAOUTn;

output			POD_CLK;
output	[15:0]	POD_DB;

input			CSn, STARTn;
output			RDn;
input	[3:0]	SEL;
output	[7:0]	DB;

output			ADC0_CSn, ADC0_DCLK;
input			ADC0_DIN;
output			ADC1_CSn, ADC1_DCLK;
input			ADC1_DIN;

/*
End of user changeable code
Part 1.
================================================================================
*/

/*
================================================================================
Beggining of user changeable code
Part 2. Definition of microprocessor generated internal control signal
*/

/* Definition of wires for LTA encoder logics */
wire			sclr_ltacnt, cnten_ltacnt;

/* Definition of wires for logic analyzer pod registers */
wire			load_podreg;

/*
End of user changeable code
Part 2.
================================================================================
*/

/* Definition of wires for interfacing processor core */
wire	[11:0]	INITA;
wire	[15:0]	INITB;

wire	[3:0]	PERIINIT;
wire	[3:0]	PERIADDRREG;
wire	[7:0]	PERICTRLREG;
wire	[15:0]	PERIVALREG;

wire	[7:0]	INTFLAG;

wire	[11:0]	PORTA;
wire	[15:0]	PORTB;

wire	[7:0]	rDIPSW;

wire	[27:0]	rA, rB;			// For direct accessing registers in microprocessor

proccore	proccore_inst (.clock(clock), .resetn(resetn),
						   .rDIPSW(rDIPSW),
						   .INITA(INITA), .INITB(INITB),
			 			   .PORTA(PORTA), .PORTB(PORTB),
			 			   .rA(rA), .rB(rB),

			 			   .INTFLAG(INTFLAG),
			 			   .PERIINIT(PERIINIT), .PERIADDRREG(PERIADDRREG),
			 			   .PERICTRLREG(PERICTRLREG), .PERIVALREG(PERIVALREG));

dipswreg	DIPSWREG1	(.clock(clock), .resetn(resetn), .DATAn(DIPSWn), .Q(rDIPSW));

/*
================================================================================
Beggining of user changeable code
Part 3. Assignment of PORTA[11:0] and PORTB[15:0]
*/

assign		gRESET_PIXELn	= PORTA[0];
assign		PHI1			= PORTA[1];
assign		PHI2			= PORTA[2];
assign		PHI3			= PORTA[3];
assign		PHI4			= PORTA[4];
assign		RESET_SUM		= PORTA[5];

assign		RDn				= PORTA[8];
assign		RESET_LOGICn	= PORTA[9];

assign		LATCH_LTAOUTn   = PORTB[1];
assign		ADV_LTAOUTn     = PORTB[2];

assign		sclr_ltacnt		= PORTB[10];
assign		cnten_ltacnt	= PORTB[11];

assign		load_podreg     = PORTB[14];
assign		POD_CLK         = PORTB[15];

assign		INITA			= 12'b0011_0000_0001;		// Initial value of PORTA
assign		INITB			= 16'b0000_0110_1100_0111;	// Initial value of PORTB

/*
End of user changeable code
Part 3.
================================================================================
*/

/*
================================================================================
Beggining of user changeable code
Part 4. Instantiation of peripheral logics
*/
wire			init_adc0, init_adc1;		// Initiating signal for serial ADCs
wire			idle_adc0, idle_adc1;		// Idlee signal of serial ADCs

wire	[7:0]	D_LTAEVEN, D_LTAODD;
wire	[15:0]	V_LTAEVEN, V_LTAODD;

ltacnt		LTACNT_EVEN	(.clock(clock), .resetn(resetn),
						 .sclr(sclr_ltacnt), .cnten(cnten_ltacnt), .load_ltalatch(DIN_LTAEVEN),
						 .Q(D_LTAEVEN));

ltacnt		LTACNT_ODD	(.clock(clock), .resetn(resetn),
						 .sclr(sclr_ltacnt), .cnten(cnten_ltacnt), .load_ltalatch(DIN_LTAODD),
						 .Q(D_LTAODD));

ad8320ctrl	adc0		(.clock(clock), .resetn(resetn),
						 .start_adc(init_adc0), .idle_adc(idle_adc0),
						 .CSn(ADC0_CSn), .DCLK(ADC0_DCLK), .DIN(ADC0_DIN),
						 .VOUT(V_LTAEVEN));

ad8320ctrl	adc1		(.clock(clock), .resetn(resetn),
						 .start_adc(init_adc1), .idle_adc(idle_adc1),
						 .CSn(ADC1_CSn), .DCLK(ADC1_DCLK), .DIN(ADC1_DIN),
						 .VOUT(V_LTAODD));
/*
End of user changeable code
Part 4.
================================================================================
*/

/*
================================================================================
Beginning of user changeable code
Part 5. Assignment of peripheral initiating signal
*/

assign		init_adc0 = PERIINIT[0];
assign		init_adc1 = PERIINIT[1];

/*
Beginning of user changeable code
Part 5. Assignment of peripheral initiating signal
================================================================================
*/

/*
================================================================================
Beginning of user changeable code
Part 6. Output mux definition
*/

/* Wire definition for output mux */
wire	[47:0]	CONC_DB;
wire	[7:0]	MUX_DB;

assign		ROW_ADDR		= rDIPSW[1:0];
assign		CONC_DB			= {
								V_LTAODD[15:0], D_LTAODD[7:0],
								V_LTAEVEN[15:0], D_LTAEVEN[7:0]
							  };

outmux		OUTMUX1		(.CSn(CSn), .SEL(SEL), .DATA(CONC_DB), .Y(MUX_DB));

opndrn		OPNDRN1		(.in(MUX_DB[0]), .out(DB[0]));
opndrn		OPNDRN2		(.in(MUX_DB[1]), .out(DB[1]));
opndrn		OPNDRN3		(.in(MUX_DB[2]), .out(DB[2]));
opndrn		OPNDRN4		(.in(MUX_DB[3]), .out(DB[3]));
opndrn		OPNDRN5		(.in(MUX_DB[4]), .out(DB[4]));
opndrn		OPNDRN6		(.in(MUX_DB[5]), .out(DB[5]));
opndrn		OPNDRN7		(.in(MUX_DB[6]), .out(DB[6]));
opndrn		OPNDRN8		(.in(MUX_DB[7]), .out(DB[7]));

/*
End of user changeable code
Part 6.
================================================================================
*/

wire	[15:0]	DATA_DB;

/*
================================================================================
Beginning of user changeable code
Part 7. Assignment of logic analyzer pod data
*/

assign			DATA_DB = {D_LTAODD, D_LTAEVEN};

/*
End of user changeable code
Part 7.
================================================================================
*/

podreg		PODREG1		(.clock(clock), .resetn(resetn), .load(load_podreg),
						 .DATA(DATA_DB),
						 .Q(POD_DB));

/*
================================================================================
Beginning of user changeable code
Part 8. Assignment of interrupt flag (INTFLAG)
*/

assign		INTFLAG = {5'b00000, idle_adc1, idle_adc0, ~STARTn};

/*
End of user changeable code
Part 8.
================================================================================
*/

endmodule